3D die packaging and die packaging containing multiple chips (“multi-chips”) has continued to receive a significant amount of attention from designers and manufacturers of electronic products. Industrial and consumer electronic products tend toward smaller size, lower cost, greater efficiency, and increased functionality. These trends place greater emphasis on the development of semiconductor packaging technologies which can accommodate denser, more complex integrated circuits in smaller packages. 3D packaging and multi-chips packaging have responded to these trends by inserting two or more silicon chips inside one package to increase functionality of the package and to achieve a “system in a package.”
Flip-chip technology is a well-developed semiconductor fabrication technology that allows the overall semiconductor package size to be made very compact by “stacking” semiconductor devices or chips. The flip-chip package configuration differs from conventional packaging configurations particularly in that it includes the mounting of a first semiconductor chip in an upside-down manner over a second substrate and electrically couples the first chip to the second substrate by means of solder bumps provided on the active surface of the first chip. Since minimal or no bonding wires are required, which would otherwise occupy additional layout space, the overall size of the flip-chip package can be made compact as compared to wirebonded types of electronic packages.
However, current methods for stacking chips pose considerable difficulties in terms of integration, manufacturing and electrical testing. In particular, current methods for 3D packaging typically include the stacking of first chips onto a wafer of multiple second chips. After wafer assembly, the stacked chips are singulated by sawing the wafer between chips. However, to prevent sawing of the overlying chips, or to prevent cracking or chipping of the overlying chips during sawing, the overlying first chips are made smaller than the underlying second chips. This necessarily restricts the dimensions of first chips that can be stacked for three-dimensional silicon integration, thus limiting the integration of the semiconductor package. Increasing the size of the underlying chip usually is not a viable solution because it is costly. Furthermore, large silicon chips experience higher stresses than small silicon chips.
Another chip stacking method includes the stacking of three or more chips on top of each other and then wirebonding the chips from different heights down to common package leads to connect the multiple chips together inside a package. However, this method poses additional drawbacks. The layout of the wirebond pads must be predetermined and oriented to prevent wires from crossing and shorting. The chips also must be thinned to fit wirebond loops within the package. In addition, stacked chips requiring wirebonds to every chip limit the extension of top chips beyond the edge of bottom chips. Moreover, thermal-compression forces onto thinned chips require a stable silicon platform that does not bend excessively during wirebonding.
In addition, present day stacking methods may pose operational problems. In other words, operation of one die in a die stack may interfere with the operation of an adjacent die in the stack. For example, a portion of an overlying or underlying chip may comprise inductive or capacitive circuits that emit high electric and/or magnetic fields. These high intensity fields may cross-couple with neighboring chips and adversely effect the operation of an adjacent chip in the stack, thus adversely affecting the operation of the semiconductor package as a whole.
Further, testing of stacked chips has proven difficult. Typically, it is necessary to test each chip in a stack separately, which involves time-intensive and often costly effort. In addition, it is often difficult to test the stack until it has already been wire-bonded and packaging has been completed. Accordingly, without the ability to test the chips before packaging, silicon chips may be blindly packaged, with yield fall-out occurring after packaging, not before packaging, as is preferred.
Accordingly, it is desirable to provide multiple-chip semiconductor device assemblies with increased functionality. In addition, it is desirable to provide multiple-chip semiconductor device assemblies in which the operation of one chip in the stack does not adversely affect the operation of another chip in the stack. It is further desirable to provide multiple-chip semiconductor device assemblies that permit accurate and efficient testing of the assemblies before packaging. It is also desirable to provide methods for fabricating such multiple-chip semiconductor device assemblies. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.